The select line S picks which input channel connects directly to output Y:
| Select Line (S) | Selected Input | Output Expression (Y) | Channel Status |
|---|---|---|---|
| 0 | I0 | Y = I0 | CONNECTED |
| 1 | I1 | Y = I1 | DISCONNECTED |
Exhaustive truth table for 2:1 Multiplexer logic: Y = I0·S̅ + I1·S
| Row | S | I0 | I1 | Active Path | Output (Y) | Active Boolean Term |
|---|---|---|---|---|---|---|
| 1 | 0 | 0 | 0 | I0 | 0 | I0·S̅ = 0 |
| 2 | 0 | 0 | 1 | I0 | 0 | I0·S̅ = 0 |
| 3 | 0 | 1 | 0 | I0 | 1 | I0·S̅ = 1 |
| 4 | 0 | 1 | 1 | I0 | 1 | I0·S̅ = 1 |
| 5 | 1 | 0 | 0 | I1 | 0 | I1·S = 0 |
| 6 | 1 | 0 | 1 | I1 | 1 | I1·S = 1 |
| 7 | 1 | 1 | 0 | I1 | 0 | I1·S = 0 |
| 8 | 1 | 1 | 1 | I1 | 1 | I1·S = 1 |
1. What is a Multiplexer?
A Multiplexer (MUX), often referred to as a Data Selector, is a combinational digital logic circuit designed to route binary information from one of several input lines to a single output line based on control signals applied to select lines.
2. Why is it called a Data Selector?
It functions similarly to a multi-position rotary switch. The select input acts as the switch control handle, directing the chosen data signal directly to the single destination output.
3. Key Pins & Signals
- Data Inputs (I0, I1): Digital binary signals (Logic 0 or Logic 1) available for selection.
- Select Line (S): The control line that determines which input is routed to the output.
- Output (Y): The single output pin that mirrors the state of the selected data input.
4. Working Principle & Boolean Expression
The fundamental logic equation for a 2:1 Multiplexer is:
• When S = 0: S̅ = 1 and S = 0, giving Y = I₀·1 + I₁·0 = I₀.
• When S = 1: S̅ = 0 and S = 1, giving Y = I₀·0 + I₁·1 = I₁.
Multiplexers scale by powers of 2. Increasing the number of data inputs requires additional select control lines according to the relation 2n : 1:
| MUX Type | Data Inputs | Select Lines | Formula | Status |
|---|---|---|---|---|
| 2 : 1 MUX | 2 (I₀, I₁) | 1 (S) | 21 : 1 | ACTIVE EXPERIMENT |
| 4 : 1 MUX | 4 (I₀ – I₃) | 2 (S₁, S₀) | 22 : 1 | Available in Module |
| 8 : 1 MUX | 8 (I₀ – I₇) | 3 (S₂, S₁, S₀) | 23 : 1 | Available in Module |
| 16 : 1 MUX | 16 (I₀ – I₁₅) | 4 (S₃ – S₀) | 24 : 1 | Available in Module |
Digital Communication
Time-Division Multiplexing (TDM) sends multiple audio/data signals over a single transmission line.
CPU Systems & ALUs
Selects between register sources, memory addresses, or operand inputs entering CPU arithmetic logic units.
Signal Routing & Buses
Routes binary data between peripheral hardware devices and central system buses without signal collision.
Data Acquisition (DAQ)
Sequentially routes analog/digital sensor signals (temperature, pressure) into a single Microcontroller ADC.
Combinational Logic Design
Implements arbitrary Boolean functions without requiring discrete gate logic arrays.
Automotive & Control Systems
Manages sensor data streams routed to the Engine Control Unit (ECU) in modern vehicles.